TXSSEL2_N=SSEL2_ASSERTED, EOF=DATA_NOT_EOF, RXIGNORE=READ_RECEIVED_DATA, TXSSEL0_N=SSEL0_ASSERTED, TXSSEL3_N=SSEL3_ASSERTED, EOT=SSEL_NOT_DEASSERTED, TXSSEL1_N=SSEL1_ASSERTED
SPI Transmit Data with Control
| TXDAT | Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. |
| TXSSEL0_N | Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. The active state of the SSEL0 pin is configured by bits in the CFG register. 0 (SSEL0_ASSERTED): SSEL0 asserted. 1 (SSEL0_NOT_ASSERTED): SSEL0 not asserted. |
| TXSSEL1_N | Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. The active state of the SSEL1 pin is configured by bits in the CFG register. 0 (SSEL1_ASSERTED): SSEL1 asserted. 1 (SSEL1_NOT_ASSERTED): SSEL1 not asserted. |
| TXSSEL2_N | Transmit Slave Select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. The active state of the SSEL2 pin is configured by bits in the CFG register. 0 (SSEL2_ASSERTED): SSEL2 asserted. 1 (SSEL2_NOT_ASSERTED): SSEL2 not asserted. |
| TXSSEL3_N | Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. The active state of the SSEL3 pin is configured by bits in the CFG register. 0 (SSEL3_ASSERTED): SSEL3 asserted. 1 (SSEL3_NOT_ASSERTED): SSEL3 not asserted. |
| EOT | End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain so for at least the time specified by the Transfer_delay value in the DLY register. 0 (SSEL_NOT_DEASSERTED): SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 1 (SSEL_DEASSERTED): SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. |
| EOF | End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. 0 (DATA_NOT_EOF): Data not EOF. This piece of data transmitted is not treated as the end of a frame. 1 (DATA_EOF): Data EOF. This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. |
| RXIGNORE | Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver.Setting this bit simplifies the transmit process and can be used with the DMA. 0 (READ_RECEIVED_DATA): Read received data. Received data must be read in order to allow transmission to progress. In slave mode, an overrun error will occur if received data is not read before new data is received. 1 (IGNORE_RECEIVED_DATA): Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| LEN | Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits in length. … 0xF = Data transfer is 16 bits in length. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |